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The Journal of Instruction-Level
Parallelism Cache Replacement Championship |
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The workshop on computer architecture competitions is a
forum for holding competitions to evaluate computer architecture research
topics. The first workshop is organized around a competition for cache
replacement algorithms. The Cache Replacement Championship (CRC) invites
contestants to submit their replacement algorithm code to participate in this
competition. Contestants will be given a fixed storage budget to implement
their best replacement algorithms on a common evaluation framework provided
by the organizing committee. Objective The goal for this competition is to compare different
cache replacement algorithms for a last level cache in a common framework.
Replacement algorithms will be evaluated for both private and shared last
level caches. The algorithms must be implemented within a fixed
storage budget as specified in the competition rules. Submissions will be
evaluated based on their performance using the framework provided by the
organizing committee. Submissions will be evaluated for two configurations: a
single-core configuration with a 1 MB last level cache, and a 4-core
configuration with a 4 MB shared last level cache. Prizes The championship has two tracks: A single-core track and
a multi-core track. The top performer for each track will receive a trophy
commemorating his/her triumph (OR some other prize to be determined later).
Top submissions will be invited to present at the workshop, when results will
be announced. All source code, write-ups and performance results will be made
publicly available through the CRC website. Authors of accepted workshop
papers will be invited to submit full papers for possible inclusion in a
special issue of the Journal of Instruction-Level Parallelism (JILP). Inclusion in the special issue will depend
on the outcome of JILP's peer-review process: invited papers will be held to
the same standard as regular submissions. Submission Requirements Each contestant is allowed a maximum of three
submissions to the competition. Each submission should include the following: o Abstract: A 300-word abstract summarizing
the submission. In addition, the abstract should include the author names,
their affiliations, and the email address of the contact author. o Paper: This will be a conference-quality
write-up of the replacement algorithm, including references to relevant
related work. The paper must clearly describe how the algorithm works, how it
is practical to implement, and how it conforms to the contest rules and fits
within the allocated storage budget. The paper must be written in English and
formatted as follows: no more than four pages, single-spaced, two-column
format, minimum 10pt Times New Roman font. The paper should be submitted in
.pdf format, and should be printable on letter-size paper with one-inch
margins on all sides. A submission will be disqualified if the paper does not
clearly describe the algorithm that corresponds to the submitted code. Papers
that do not conform to the length and format rules will only be reviewed at
the discretion of the program committee. If a contestant has two or three
similar submissions (e.g., only differ in table sizes or little tweaks to the
algorithm), he/she should submit only one paper for all submissions. However,
if the two or three submissions by one contestant are totally different,
he/she should submit a paper for each submission. o Cache Replacement code: A single C++ header file that
can be included in the provided infrastructure must be submitted along with
the paper as a separate file. This code must be well commented so that it can
be understood and evaluated. Unreadable or insufficiently documented code
will be rejected by the program committee. The file sample_cacherepl.h from
the infrastructure is distributed with a default true LRU replacement
algorithm, and should be replaced with the contestant’s code. The code should
be compiled and run on the existing infrastructure without changing any code
or Makefile, and should NOT require any library code that is not part of C++. More details on how to submit these files will be
available before the submission deadline. Competition
Rules The competition will proceed as follows. Contestants are
responsible for implementing and evaluating their algorithm in the
distributed framework. The framework itself is provided as a binary and
cannot be modified (except for the header file that implements the cache
replacement algorithm). Submissions will be taken, compiled and run with the
original version of the framework. The contestants will be ranked on the
basis of the measured performance of their replacement algorithms. Each
contestant will get a score for each of the two configurations evaluated in
the competition. In the single-core track, the score represents the geometric
mean of their replacement algorithm speedups across a set of (undistributed)
benchmarks. In the multi-core track, the score represents the geometric mean
of the replacement algorithms weighted speedup across a set of
(undistributed) multi-program and multi-threaded benchmarks. The distributed
simulation framework would enable contestants to build their own benchmark
files for use with the simulator. Acceptance Criteria In the interest of assembling a quality program for
workshop attendees and future readers, there will be an overall selection
process, of which performance ranking is the primary component. To be
considered, submissions must conform to the submission requirements described
above. Submissions will be selected to appear in the workshop on the basis of
the performance ranking, novelty, and overall quality of the paper and
commented code. Novelty is not a strict requirement, for example, a
contestant may submit his/her previously published design or make incremental
enhancements to previously proposed design. In such cases, performance is a
heavily weighted criterion, as is overall quality of the paper (for example,
analysis of new results on the common framework, etc.). Description of the Simulation
Infrastructure CRC
Kit: Download and Directions Important Dates
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Steering Committee Alaa
R. Alameldeen, Intel Eric
Rotenberg, NC State Organizing Committee Alaa R. Alameldeen, Intel Aamer Jaleel, Intel Moinuddin
Qureshi, IBM Program Chair Joel
Emer, Intel Program Committee Doug
Burger, Microsoft Mainak
Chaudhuri, IITK Aamer
Jaleel, Intel Gabriel
Loh, Georgia Tech Moinuddin
Qureshi, IBM |
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